(A) Field of the Invention
The present invention relates to a method for configuring a combinational switching matrix and a testing system for semiconductor devices using the same, and more particularly, to a method for configuring a combinational switching matrix incorporating a plurality of switching modules, and a testing system for semiconductor devices using the same.
(B) Description of the Related Art
Generally, it is necessary to test the electrical characteristics of semiconductor device such as the integrated circuit devices at the wafer level to check whether the integrated circuit device meets the product specifications. Integrated circuit devices with electrical characteristics meeting the specifications are selected for the subsequent packaging process, while other devices are discarded to avoid additional packaging cost. Another electrical property test is performed on the integrated circuit device after the packaging process is completed, so as to screen out substandard devices and increase product quality.
Electronic instrumentations comprising of different types and quantity of measurement resources are used to test and analyze the performance of devices, and circuits on the wafer. A plurality of test leads from the measurement resources are connected to selected points, within the device or circuit on the wafer in order to perform the desired tests. Conventionally, a customized or generic switching matrix or multiplexer is used to easily change the connections between test instruments and multiple or single device under test (DUT). The switching matrix is configured to connect input ports to output ports in arbitrary combinations in accordance with an instruction from a user. At wafer-level, depending on the electric properties being measured, one or more test instruments are connected to the input ports, a probe card is connected to the output ports, and the target DUT is connected to the probe card. The input ports and the output ports are connected via relay switches that builds up the connection path within the matrix or multiplexer, and the electrical connections between the input ports and the output ports are opened or closed by the relay switches. The above description is also applicable to package-level test in which devices or circuits are tested with the use of sockets on printed circuit board that link it to the instruments directly or via a matrix and/or multiplexer. U.S. Pat. No. 6,069,484, U.S. Pat. No. 5,124,638, U.S. Pat. No. 5,559,482, U.S. Pat. No. 6,791,344, and U.S. Pat. No. 6,100,815 disclose the application of the switching matrix to the testing of the integrated circuit devices.